The present invention relates generally to the formation of integrated circuit structures, and particularly, but not by way of limitation, to methods for forming openings in damascene structures. More particularly, the present invention relates to methods for forming openings in dual damascene structures using plug materials having varied etching rates.
As semiconductor wafers continually progress to higher density chips with shrinking geometries of 0.13 μm and below, the materials and processes used in wafer fabrication are undergoing dramatic changes. There is a concurrent scaling of all device features to maintain electrical performance. This trend is made possible by the development of new manufacturing techniques as well as innovative improvements of existing procedures thereby extending their utility further towards miniaturization and higher density. One area where the limits of technology are constantly tested is the formation of via, trench, and contact openings in low-k material or dielectric layers on semiconductor substrates and these openings having submicron geometries represent one of the smallest microlithographically defined features on the integrated circuit. These openings pass through the various dielectric layers and are filled with conductive material to form interconnections. One such process for forming interconnections is the ubiquitous dual damascene process.
While dual damascene methods are desirable in semiconductor device fabrication, dual damascene methods are nonetheless not entirely without problems. The type of plug materials used in dual-damascene processes often determine the final trench and via opening profiles. FIG. 1a illustrates a cross-sectional view of a portion of a prior art method of forming a dual damascene structure and where use of a low-etching rate plug material typically produces undesirable trench and via opening profiles. A semiconductor substrate (not shown) is provided with a etch stop layer 10 and a low-k material layer 20 formed thereabove and a plug 30 having a low etching rate is formed in a via opening of the dual damascene structure. A patterned photoresist layer 50 and an anti-reflective coating layer 40 are formed above the plug 30. As shown in FIG. 1b, in the formation of the trench of the dual damascene structure, it is typically observed that an undesirable fence profile 60 is produced as a result of the higher etching rate of low-k material layer 20 with respect to plug 30 such that low-k material layer 20 is etched faster. In forming the trench opening, the trench opening is incompletely etched leaving a fence of unetched material around the via opening and a layer of unetched material overlying the plug 30. As a result, improperly formed dual damascene structures lead to a deterioration of electrical properties, electrical opens, and/or lowering of yield for the semiconductor devices.
FIG. 2a illustrates a cross-sectional view of a portion of a prior art method of forming a dual damascene structure and how use of a high-etching rate plug material produces undesirable trench and via opening profiles. A semiconductor substrate (not shown) is provided with an etch stop layer 10 and a low-k material layer 20 formed thereabove and a plug 30 having a high-etching rate is formed in a via opening of the dual damascene structure. A patterned photoresist layer 50 and an anti-reflective coating layer 40 are formed above the plug 30. As shown in FIG. 2b, undesirable facet profile 70 and etch stop layer break 80 are typically produced as a result of the higher etching rate of plug 30 with respect to low-k material layer 20 such that low-k material layer 20 is etched slower. Dual damascene structures having these fence and facet profiles and etch stop layer breaks exhibit increased RC delay which in turn degrade circuit performance and contribute to low yield for the semiconductor devices.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for improved methods of forming damascene structures that do not have the fence/facet profiles or etch stop layer breaks that contribute to increased RC delay characteristics and reliability and IC performance problems associated with conventional methods of forming dual damascene structures.